mux - VHDL: muxes between 11 buses 8 bits wide output -

i recieved question pre interview question "draw diagram , write vhdl code module meets following requirements: a. synchronous. b. muxes between 11 buses each bus 8-bits wide. c. has 2 cycles of latency. d. optimized maximum clock frequency."

ive been trying myself reading old notes , assignments have done in university don't think i'm on right track this. have code soo far posted below:

 library ieee; use ieee.std_logic_1164.all;  entity mux port(   a:  in std_logic_vector(7 downto 0);   b:  in std_logic_vector(7 downto 0);   c:  in std_logic_vector(7 downto 0);   d:  in std_logic_vector(7 downto 0);   e:  in std_logic_vector(7 downto 0);   f:  in std_logic_vector(7 downto 0);   g:  in std_logic_vector(7 downto 0);   h:  in std_logic_vector(7 downto 0);   i:  in std_logic_vector(7 downto 0);   j:  in std_logic_vector(7 downto 0);   k:  in std_logic_vector(7 downto 0);  s0: in std_logic_vector(3 downto 0);   z: out std_logic_vector(7 downto 0) );  end mux; architecture func of mux begin process (a,b,c,d,e,f,g,h,i,j,k,s0) begin      if s0="0001"         z<= a;     elsif s0="0010"         z<= b;     elsif s0="0011"         z<= c;     elsif s0="0100"         z<= d;     elsif s0="0101"         z<= e;     elsif s0="0110"         z<= f;     elsif s0="0111"         z<= g;     elsif s0="1000"         z<= h;     elsif s0="1001"         z<= i;     elsif s0="1010"         z<= j;     elsif s0="1011"         z<= k;       else          z<=a;     end if;   end process; end func; 

and code have second file:

 library ieee;  use ieee.std_logic_1164.all;  use ieee.std_logic_arith.all;  entity mux11test  end entity mux11test;  architecture test of mux11test   signal    t_a:  std_logic_vector(7 downto 0):="00000001";    signal    t_b:  std_logic_vector(7 downto 0):="00000010";   signal    t_c:  std_logic_vector(7 downto 0):="00000011";   signal    t_d:  std_logic_vector(7 downto 0):="00000100";   signal    t_e:  std_logic_vector(7 downto 0):="00000101";   signal    t_f:  std_logic_vector(7 downto 0):="00000110";   signal    t_g:  std_logic_vector(7 downto 0):="00000111";   signal    t_h:  std_logic_vector(7 downto 0):="00001000";   signal    t_i:  std_logic_vector(7 downto 0):="00001001";   signal    t_j:  std_logic_vector(7 downto 0):="00001010";   signal    t_k:  std_logic_vector(7 downto 0):="00001011";     signal    t_s: std_logic_vector( 3 downto 0);  signal    t_z:  std_logic_vector(7 downto 0);  component mux11 port(   a:  in std_logic_vector(7 downto 0);   b:  in std_logic_vector(7 downto 0);   c:  in std_logic_vector(7 downto 0);   d:  in std_logic_vector(7 downto 0);   e:  in std_logic_vector(7 downto 0);   f:  in std_logic_vector(7 downto 0);   g:  in std_logic_vector(7 downto 0);   h:  in std_logic_vector(7 downto 0);   i:  in std_logic_vector(7 downto 0);   j:  in std_logic_vector(7 downto 0);   k:  in std_logic_vector(7 downto 0);  s0: in std_logic_vector(3 downto 0);   z:  out std_logic_vector(7 downto 0)   );  end component ; signal clk : std_logic; constant clk_period: time:=100ns; begin  umux: mux11 port map(t_a,t_b,t_c,t_d,t_e,t_f,t_g,t_h,t_i,t_j,t_k,t_s,t_z); clk_process:process  begin clk<='0'; wait clk_period/2; clk <='1'; wait clk_period/2; end process; process begin if t_s="0001"     t_z <= t_a ; elsif  t_s="0010"   t_z <= t_b ; wait 100 ns;  elsif  t_s="0011" t_z <= t_c ; wait 100 ns;  elsif  t_s="0100" t_z  <= t_d ; wait 100 ns; elsif  t_s="0101" t_z  <=t_e ; wait 100 ns; elsif  t_s="0110" t_z <=  t_f ; wait 100 ns;     elsif  t_s="0111" t_z  <= t_g ; wait 100 ns;     elsif  t_s="1000" t_z  <= t_h ; wait 100 ns; elsif  t_s="1001" t_z  <= t_i ; wait 100 ns; elsif  t_s="1010" t_z  <= t_j ; wait 100 ns; elsif  t_s="1011" t_z <= t_k ; wait 100 ns;   wait;  end if; end process;  end architecture test; 

is there tell me if im on right path , if synchronous , how start implementing or determining 2 cycles of latency?

i try write clear answer you.

first of need clock in design let's call clk.

entity mux port(    clk: in std_logic;   a:  in std_logic_vector(7 downto 0);   b:  in std_logic_vector(7 downto 0);   c:  in std_logic_vector(7 downto 0);   d:  in std_logic_vector(7 downto 0);   e:  in std_logic_vector(7 downto 0);   f:  in std_logic_vector(7 downto 0);   g:  in std_logic_vector(7 downto 0);   h:  in std_logic_vector(7 downto 0);   i:  in std_logic_vector(7 downto 0);   j:  in std_logic_vector(7 downto 0);   k:  in std_logic_vector(7 downto 0);   s0: in std_logic_vector(3 downto 0);    z: out std_logic_vector(7 downto 0));  end mux; 

the idea when use synchronous processes update values on edge of clock. let's rising edge. processes have sensitive input clk.

p : process (clk) begin    if (rising_edge(clk))      ...    end if; end process; 

concerning multiplexer, idea good. yet suggest use case statement because easier read if elsif.

case s0     when "0001"  => z <= a;     when "0010"  => z <= b;     ...     when "1011"  => z <= k; end case; 

edit : since forgot talk 2 cycles latency i'll 2 words. there need 2 intermediate signals (ie z_i , z_ii). z_ii takes z_i after 1 clock cycle , z takes z_ii after 1 clock cycle.

z_ii <= z_i; z    <= z_ii; 

of course need drive z_i (and not z) in process.